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https://github.com/checkpoint-restore/criu.git
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73b9a2ebe3
On Wed, Oct 01, 2014 at 05:51:09PM +0400, Pavel Emelyanov wrote: > > Yes, what you've been expecting? > > if (!strcmp(argv[optind])) > return cpu_cap_check() > > or smth like this. updated. So if it become confusing -- feel free to merge [1;9] and ping me to resend the rest, or pick up from attachements. >From 6af96ff63ac82f9566c3cba9c116dc67698c9797 Mon Sep 17 00:00:00 2001 From: Cyrill Gorcunov <gorcunov@openvz.org> Date: Tue, 30 Sep 2014 18:33:40 +0400 Subject: [PATCH] cpuinfo: Add "cpuinfo [dump|check]" commands They allow to validate cpuinfo information without running complete dump/restore actions. Signed-off-by: Cyrill Gorcunov <gorcunov@openvz.org> Signed-off-by: Pavel Emelyanov <xemul@parallels.com>
207 lines
8.5 KiB
C
207 lines
8.5 KiB
C
#ifndef __CR_ASM_CPU_H__
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#define __CR_ASM_CPU_H__
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#include "asm/types.h"
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/*
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* Adopted from linux kernel and enhanced from Intel/AMD manuals.
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*/
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#define NCAPINTS (12) /* N 32-bit words worth of info */
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#define NCAPINTS_BITS (NCAPINTS * 32)
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#define X86_FEATURE_FPU (0*32+ 0) /* Onboard FPU */
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#define X86_FEATURE_VME (0*32+ 1) /* Virtual 8086 Mode Enhancements */
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#define X86_FEATURE_DE (0*32+ 2) /* Debugging Extensions */
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#define X86_FEATURE_PSE (0*32+ 3) /* Page Size Extension */
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#define X86_FEATURE_TSC (0*32+ 4) /* Time Stamp Counter */
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#define X86_FEATURE_MSR (0*32+ 5) /* Model Specific Registers RDMSR and WRMSR Instructions */
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#define X86_FEATURE_PAE (0*32+ 6) /* Physical Address Extension */
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#define X86_FEATURE_MCE (0*32+ 7) /* Machine Check Exception */
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#define X86_FEATURE_CX8 (0*32+ 8) /* CMPXCHG8 instruction */
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#define X86_FEATURE_APIC (0*32+ 9) /* APIC On-Chip */
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#define X86_FEATURE_SEP (0*32+11) /* SYSENTER and SYSEXIT Instructions */
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#define X86_FEATURE_MTRR (0*32+12) /* Memory Type Range Registers */
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#define X86_FEATURE_PGE (0*32+13) /* PTE Global Bit */
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#define X86_FEATURE_MCA (0*32+14) /* Machine Check Architecture */
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#define X86_FEATURE_CMOV (0*32+15) /* CMOV instructions (plus FCMOVcc, FCOMI with FPU) */
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#define X86_FEATURE_PAT (0*32+16) /* Page Attribute Table */
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#define X86_FEATURE_PSE36 (0*32+17) /* 36-Bit Page Size Extension */
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#define X86_FEATURE_PSN (0*32+18) /* Processor Serial Number */
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#define X86_FEATURE_DS (0*32+21) /* Debug Store */
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#define X86_FEATURE_CLFLUSH (0*32+19) /* CLFLUSH instruction */
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#define X86_FEATURE_ACPI (0*32+22) /* Thermal Monitor and Software Controlled Clock Facilities */
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#define X86_FEATURE_MMX (0*32+23) /* Multimedia Extensions */
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#define X86_FEATURE_FXSR (0*32+24) /* FXSAVE/FXRSTOR, CR4.OSFXSR */
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#define X86_FEATURE_XMM (0*32+25) /* "sse" */
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#define X86_FEATURE_XMM2 (0*32+26) /* "sse2" */
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#define X86_FEATURE_SS (0*32+27) /* Self Snoop */
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#define X86_FEATURE_HTT (0*32+28) /* Multi-Threading */
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#define X86_FEATURE_TM (0*32+29) /* Thermal Monitor */
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#define X86_FEATURE_PBE (0*32+31) /* Pending Break Enable */
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#define X86_FEATURE_SYSCALL (1*32+11) /* SYSCALL/SYSRET */
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#define X86_FEATURE_MMXEXT (1*32+22) /* AMD MMX extensions */
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#define X86_FEATURE_RDTSCP (1*32+27) /* RDTSCP */
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#define X86_FEATURE_3DNOWEXT (1*32+30) /* AMD 3DNow! extensions */
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#define X86_FEATURE_3DNOW (1*32+31) /* 3DNow! */
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#define X86_FEATURE_REP_GOOD (3*32+16) /* rep microcode works well */
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#define X86_FEATURE_NOPL (3*32+20) /* The NOPL (0F 1F) instructions */
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#define X86_FEATURE_XMM3 (4*32+ 0) /* "pni" SSE-3 */
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#define X86_FEATURE_PCLMULQDQ (4*32+ 1) /* PCLMULQDQ instruction */
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#define X86_FEATURE_DTES64 (4*32+ 2) /* 64-bit DS Area */
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#define X86_FEATURE_MWAIT (4*32+ 3) /* "monitor" Monitor/Mwait support */
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#define X86_FEATURE_DSCPL (4*32+ 4) /* CPL Qualified Debug Store */
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#define X86_FEATURE_VMX (4*32+ 5) /* Virtual Machine Extensions */
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#define X86_FEATURE_SMX (4*32+ 6) /* Safer Mode Extensions */
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#define X86_FEATURE_EST (4*32+ 7) /* Enhanced Intel SpeedStep technology */
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#define X86_FEATURE_TM2 (4*32+ 8) /* Thermal Monitor 2 */
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#define X86_FEATURE_SSSE3 (4*32+ 9) /* Supplemental SSE-3 */
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#define X86_FEATURE_CNXTID (4*32+10) /* L1 Context ID */
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#define X86_FEATURE_FMA (4*32+12) /* Fused multiply-add */
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#define X86_FEATURE_CX16 (4*32+13) /* CMPXCHG16B */
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#define X86_FEATURE_XTPR_UCTL (4*32+14) /* xTPR Update Control */
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#define X86_FEATURE_PDCM (4*32+15) /* Perfmon and Debug Capability */
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#define X86_FEATURE_PCID (4*32+17) /* Process-context identifiers */
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#define X86_FEATURE_DCA (4*32+18) /* Ability to prefetch data from a memory mapped device */
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#define X86_FEATURE_XMM4_1 (4*32+19) /* "sse4_1" SSE-4.1 */
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#define X86_FEATURE_XMM4_2 (4*32+20) /* "sse4_2" SSE-4.2 */
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#define X86_FEATURE_X2APIC (4*32+21) /* x2APIC */
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#define X86_FEATURE_MOVBE (4*32+22) /* MOVBE instruction */
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#define X86_FEATURE_POPCNT (4*32+23) /* POPCNT instruction */
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#define X86_FEATURE_TSCDL (4*32+24) /* Local APIC timer supports one-shot operation using a TSC deadline value */
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#define X86_FEATURE_AES (4*32+25) /* AES instructions */
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#define X86_FEATURE_XSAVE (4*32+26) /* XSAVE/XRSTOR/XSETBV/XGETBV */
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#define X86_FEATURE_OSXSAVE (4*32+27) /* "" XSAVE enabled in the OS */
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#define X86_FEATURE_AVX (4*32+28) /* Advanced Vector Extensions */
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#define X86_FEATURE_F16C (4*32+29) /* 16-bit fp conversions */
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#define X86_FEATURE_RDRAND (4*32+30) /* The RDRAND instruction */
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#define X86_FEATURE_ABM (6*32+ 5) /* Advanced bit manipulation */
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#define X86_FEATURE_SSE4A (6*32+ 6) /* SSE-4A */
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#define X86_FEATURE_MISALIGNSSE (6*32+ 7) /* Misaligned SSE mode */
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#define X86_FEATURE_3DNOWPREFETCH (6*32+ 8) /* 3DNow prefetch instructions */
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#define X86_FEATURE_XOP (6*32+11) /* extended AVX instructions */
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#define X86_FEATURE_FMA4 (6*32+16) /* 4 operands MAC instructions */
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#define X86_FEATURE_TBM (6*32+21) /* trailing bit manipulations */
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#define X86_FEATURE_FSGSBASE (9*32+ 0) /* Supports RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE */
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#define X86_FEATURE_BMI1 (9*32+ 3) /* 1st group bit manipulation extensions */
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#define X86_FEATURE_HLE (9*32+ 4) /* Hardware Lock Elision */
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#define X86_FEATURE_AVX2 (9*32+ 5) /* AVX2 instructions */
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#define X86_FEATURE_SMEP (9*32+ 7) /* Supervisor Mode Execution Protection */
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#define X86_FEATURE_BMI2 (9*32+ 8) /* 2nd group bit manipulation extensions */
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#define X86_FEATURE_ERMS (9*32+ 9) /* Enhanced REP MOVSB/STOSB */
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#define X86_FEATURE_INVPCID (9*32+10) /* Invalidate Processor Context ID */
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#define X86_FEATURE_RTM (9*32+11) /* Restricted Transactional Memory */
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#define X86_FEATURE_MPX (9*32+14) /* Memory Protection Extension */
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#define X86_FEATURE_AVX512F (9*32+16) /* AVX-512 Foundation */
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#define X86_FEATURE_AVX512DQ (9*32+17) /* AVX-512 Foundation */
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#define X86_FEATURE_RDSEED (9*32+18) /* The RDSEED instruction */
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#define X86_FEATURE_ADX (9*32+19) /* The ADCX and ADOX instructions */
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#define X86_FEATURE_SMAP (9*32+20) /* Supervisor Mode Access Prevention */
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#define X86_FEATURE_CLFLUSHOPT (9*32+23) /* CLFLUSHOPT instruction */
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#define X86_FEATURE_IPT (9*32+25) /* Intel Processor Trace */
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#define X86_FEATURE_AVX512PF (9*32+26) /* AVX-512 Prefetch */
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#define X86_FEATURE_AVX512ER (9*32+27) /* AVX-512 Exponential and Reciprocal */
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#define X86_FEATURE_AVX512CD (9*32+28) /* AVX-512 Conflict Detection */
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#define X86_FEATURE_SHA (9*32+29) /* Intel SHA extensions */
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#define X86_FEATURE_AVX512BW (9*32+30) /* AVX-512 */
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#define X86_FEATURE_AVXVL (9*32+31) /* AVX-512 */
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#define X86_FEATURE_XSAVEOPT (10*32+0) /* XSAVEOPT */
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#define X86_FEATURE_XSAVEC (10*32+1) /* XSAVEC */
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#define X86_FEATURE_XGETBV1 (10*32+2) /* XGETBV with ECX = 1 */
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#define X86_FEATURE_XSAVES (10*32+3) /* XSAVES/XRSTORS */
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/*
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* Node 11 is our own, kernel has not such entry.
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*/
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#define X86_FEATURE_PREFETCHWT1 (11*32+0) /* The PREFETCHWT1 instruction */
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static inline void native_cpuid(unsigned int *eax, unsigned int *ebx,
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unsigned int *ecx, unsigned int *edx)
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{
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/* ecx is often an input as well as an output. */
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asm volatile("cpuid"
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: "=a" (*eax),
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"=b" (*ebx),
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"=c" (*ecx),
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"=d" (*edx)
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: "0" (*eax), "2" (*ecx)
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: "memory");
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}
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static inline void cpuid(unsigned int op,
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unsigned int *eax, unsigned int *ebx,
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unsigned int *ecx, unsigned int *edx)
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{
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*eax = op;
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*ecx = 0;
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native_cpuid(eax, ebx, ecx, edx);
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}
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static inline void cpuid_count(unsigned int op, int count,
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unsigned int *eax, unsigned int *ebx,
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unsigned int *ecx, unsigned int *edx)
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{
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*eax = op;
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*ecx = count;
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native_cpuid(eax, ebx, ecx, edx);
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}
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static inline unsigned int cpuid_eax(unsigned int op)
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{
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unsigned int eax, ebx, ecx, edx;
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cpuid(op, &eax, &ebx, &ecx, &edx);
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return eax;
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}
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static inline unsigned int cpuid_ecx(unsigned int op)
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{
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unsigned int eax, ebx, ecx, edx;
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cpuid(op, &eax, &ebx, &ecx, &edx);
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return ecx;
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}
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static inline unsigned int cpuid_edx(unsigned int op)
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{
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unsigned int eax, ebx, ecx, edx;
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cpuid(op, &eax, &ebx, &ecx, &edx);
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return edx;
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}
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#define X86_FEATURE_VERSION 1
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enum {
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X86_VENDOR_INTEL = 0,
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X86_VENDOR_AMD = 1,
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X86_VENDOR_MAX
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};
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struct cpuinfo_x86 {
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u8 x86_family;
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u8 x86_vendor;
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u8 x86_model;
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u8 x86_mask;
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u32 x86_capability[NCAPINTS];
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u32 extended_cpuid_level;
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int cpuid_level;
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char x86_vendor_id[16];
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char x86_model_id[64];
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};
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extern bool cpu_has_feature(unsigned int feature);
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extern int cpu_init(void);
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extern int cpu_dump_cpuinfo(void);
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extern int cpu_validate_cpuinfo(void);
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extern int cpuinfo_dump(void);
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extern int cpuinfo_check(void);
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#endif /* __CR_CPU_H__ */
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