mirror of
https://github.com/checkpoint-restore/criu.git
synced 2026-07-30 05:21:57 +00:00
e29c9daec2
Current code doesn't make any difference between OPT and no-OPT except for the message is printed or not in the open_image(). So this particular change changes nothing but the availability of this message. In the next patches I wil introduce "empty images" to deal with the ENOENT situation in a more graceful manner. Signed-off-by: Pavel Emelyanov <xemul@parallels.com>
491 lines
12 KiB
C
491 lines
12 KiB
C
#include <stdio.h>
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#include <stdlib.h>
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#include <unistd.h>
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#include <errno.h>
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#include <string.h>
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#include <sys/types.h>
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#include "asm/bitops.h"
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#include "asm/types.h"
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#include "asm/cpu.h"
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#include "asm/fpu.h"
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#include "compiler.h"
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#include "cr_options.h"
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#include "proc_parse.h"
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#include "util.h"
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#include "log.h"
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#include "cpu.h"
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#include "protobuf.h"
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#include "protobuf/cpuinfo.pb-c.h"
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#undef LOG_PREFIX
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#define LOG_PREFIX "cpu: "
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static struct cpuinfo_x86 rt_cpu_info;
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static void set_cpu_cap(struct cpuinfo_x86 *c, unsigned int feature)
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{
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if (likely(feature < NCAPINTS_BITS))
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set_bit(feature, (unsigned long *)c->x86_capability);
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}
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static void clear_cpu_cap(struct cpuinfo_x86 *c, unsigned int feature)
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{
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if (likely(feature < NCAPINTS_BITS))
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clear_bit(feature, (unsigned long *)c->x86_capability);
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}
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static int test_cpu_cap(struct cpuinfo_x86 *c, unsigned int feature)
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{
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if (likely(feature < NCAPINTS_BITS))
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return test_bit(feature, (unsigned long *)c->x86_capability);
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return 0;
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}
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bool cpu_has_feature(unsigned int feature)
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{
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return test_cpu_cap(&rt_cpu_info, feature);
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}
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static int cpu_init_cpuid(struct cpuinfo_x86 *c)
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{
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/*
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* See cpu_detect() in the kernel, also
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* read cpuid specs not only from general
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* SDM but for extended instructions set
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* reference.
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*/
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/* Get vendor name */
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cpuid(0x00000000,
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(unsigned int *)&c->cpuid_level,
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(unsigned int *)&c->x86_vendor_id[0],
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(unsigned int *)&c->x86_vendor_id[8],
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(unsigned int *)&c->x86_vendor_id[4]);
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if (!strcmp(c->x86_vendor_id, "GenuineIntel")) {
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c->x86_vendor = X86_VENDOR_INTEL;
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} else if (!strcmp(c->x86_vendor_id, "AuthenticAMD")) {
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c->x86_vendor = X86_VENDOR_AMD;
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} else {
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pr_err("Unsupported CPU vendor %s\n",
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c->x86_vendor_id);
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return -1;
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}
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c->x86_family = 4;
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/* Intel-defined flags: level 0x00000001 */
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if (c->cpuid_level >= 0x00000001) {
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u32 eax, ebx, ecx, edx;
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cpuid(0x00000001, &eax, &ebx, &ecx, &edx);
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c->x86_family = (eax >> 8) & 0xf;
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c->x86_model = (eax >> 4) & 0xf;
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c->x86_mask = eax & 0xf;
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if (c->x86_family == 0xf)
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c->x86_family += (eax >> 20) & 0xff;
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if (c->x86_family >= 0x6)
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c->x86_model += ((eax >> 16) & 0xf) << 4;
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c->x86_capability[0] = edx;
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c->x86_capability[4] = ecx;
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}
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/* Additional Intel-defined flags: level 0x00000007 */
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if (c->cpuid_level >= 0x00000007) {
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u32 eax, ebx, ecx, edx;
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cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx);
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c->x86_capability[9] = ebx;
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c->x86_capability[11] = ecx;
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}
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/* Extended state features: level 0x0000000d */
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if (c->cpuid_level >= 0x0000000d) {
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u32 eax, ebx, ecx, edx;
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cpuid_count(0x0000000d, 1, &eax, &ebx, &ecx, &edx);
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c->x86_capability[10] = eax;
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}
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/* AMD-defined flags: level 0x80000001 */
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c->extended_cpuid_level = cpuid_eax(0x80000000);
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if ((c->extended_cpuid_level & 0xffff0000) == 0x80000000) {
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if (c->extended_cpuid_level >= 0x80000001) {
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c->x86_capability[1] = cpuid_edx(0x80000001);
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c->x86_capability[6] = cpuid_ecx(0x80000001);
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}
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}
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/*
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* We're don't care about scattered features for now,
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* otherwise look into init_scattered_cpuid_features()
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* in kernel.
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*/
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if (c->extended_cpuid_level >= 0x80000004) {
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unsigned int *v;
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char *p, *q;
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v = (unsigned int *)c->x86_model_id;
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cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
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cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
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cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
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c->x86_model_id[48] = 0;
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/*
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* Intel chips right-justify this string for some dumb reason;
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* undo that brain damage:
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*/
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p = q = &c->x86_model_id[0];
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while (*p == ' ')
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p++;
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if (p != q) {
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while (*p)
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*q++ = *p++;
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while (q <= &c->x86_model_id[48])
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*q++ = '\0'; /* Zero-pad the rest */
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}
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}
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/* On x86-64 NOP is always present */
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set_cpu_cap(c, X86_FEATURE_NOPL);
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switch (c->x86_vendor) {
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case X86_VENDOR_INTEL:
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/*
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* Strictly speaking we need to read MSR_IA32_MISC_ENABLE
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* here but on ring3 it's impossible.
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*/
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if (c->x86_family == 15) {
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clear_cpu_cap(c, X86_FEATURE_REP_GOOD);
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clear_cpu_cap(c, X86_FEATURE_ERMS);
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} else if (c->x86_family == 6) {
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/* On x86-64 rep is fine */
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set_cpu_cap(c, X86_FEATURE_REP_GOOD);
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}
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/* See filter_cpuid_features in kernel */
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if ((s32)c->cpuid_level < (s32)0x0000000d)
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clear_cpu_cap(c, X86_FEATURE_XSAVE);
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break;
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case X86_VENDOR_AMD:
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/*
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* Bit 31 in normal CPUID used for nonstandard 3DNow ID;
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* 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway
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*/
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clear_cpu_cap(c, 0 * 32 + 31);
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if (c->x86_family >= 0x10)
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set_cpu_cap(c, X86_FEATURE_REP_GOOD);
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if (c->x86_family == 0xf) {
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u32 level;
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/* On C+ stepping K8 rep microcode works well for copy/memset */
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level = cpuid_eax(1);
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if ((level >= 0x0f48 && level < 0x0f50) || level >= 0x0f58)
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set_cpu_cap(c, X86_FEATURE_REP_GOOD);
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}
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break;
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}
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return 0;
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}
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int cpu_init(void)
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{
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if (cpu_init_cpuid(&rt_cpu_info))
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return -1;
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BUILD_BUG_ON(sizeof(struct xsave_struct) != XSAVE_SIZE);
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BUILD_BUG_ON(sizeof(struct i387_fxsave_struct) != FXSAVE_SIZE);
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/*
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* Make sure that at least FPU is onboard
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* and fxsave is supported.
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*/
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if (cpu_has_feature(X86_FEATURE_FPU)) {
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if (!cpu_has_feature(X86_FEATURE_FXSR)) {
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pr_err("missing support fxsave/restore insns\n");
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return -1;
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}
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}
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pr_debug("fpu:%d fxsr:%d xsave:%d\n",
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!!cpu_has_feature(X86_FEATURE_FPU),
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!!cpu_has_feature(X86_FEATURE_FXSR),
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!!cpu_has_feature(X86_FEATURE_XSAVE));
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return 0;
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}
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int cpu_dump_cpuinfo(void)
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{
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CpuinfoEntry cpu_info = CPUINFO_ENTRY__INIT;
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CpuinfoX86Entry cpu_x86_info = CPUINFO_X86_ENTRY__INIT;
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CpuinfoX86Entry *cpu_x86_info_ptr = &cpu_x86_info;
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struct cr_img *img;
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img = open_image(CR_FD_CPUINFO, O_DUMP);
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if (!img)
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return -1;
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cpu_info.x86_entry = &cpu_x86_info_ptr;
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cpu_info.n_x86_entry = 1;
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cpu_x86_info.vendor_id = (rt_cpu_info.x86_vendor == X86_VENDOR_INTEL) ?
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CPUINFO_X86_ENTRY__VENDOR__INTEL :
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CPUINFO_X86_ENTRY__VENDOR__AMD;
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cpu_x86_info.cpu_family = rt_cpu_info.x86_family;
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cpu_x86_info.model = rt_cpu_info.x86_model;
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cpu_x86_info.stepping = rt_cpu_info.x86_mask;
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cpu_x86_info.capability_ver = 1;
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cpu_x86_info.n_capability = ARRAY_SIZE(rt_cpu_info.x86_capability);
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cpu_x86_info.capability = (void *)rt_cpu_info.x86_capability;
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if (rt_cpu_info.x86_model_id[0])
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cpu_x86_info.model_id = rt_cpu_info.x86_model_id;
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if (pb_write_one(img, &cpu_info, PB_CPUINFO) < 0) {
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close_image(img);
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return -1;
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}
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close_image(img);
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return 0;
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}
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#define __ins_bit(__l, __v) (1u << ((__v) - 32u * (__l)))
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static u32 x86_ins_capability_mask[NCAPINTS] = {
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[0] =
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__ins_bit(0, X86_FEATURE_FPU) |
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__ins_bit(0, X86_FEATURE_TSC) |
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__ins_bit(0, X86_FEATURE_CX8) |
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__ins_bit(0, X86_FEATURE_SEP) |
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__ins_bit(0, X86_FEATURE_CMOV) |
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__ins_bit(0, X86_FEATURE_CLFLUSH) |
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__ins_bit(0, X86_FEATURE_MMX) |
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__ins_bit(0, X86_FEATURE_FXSR) |
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__ins_bit(0, X86_FEATURE_XMM) |
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__ins_bit(0, X86_FEATURE_XMM2),
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[1] =
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__ins_bit(1, X86_FEATURE_SYSCALL) |
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__ins_bit(1, X86_FEATURE_MMXEXT) |
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__ins_bit(1, X86_FEATURE_RDTSCP) |
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__ins_bit(1, X86_FEATURE_3DNOWEXT) |
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__ins_bit(1, X86_FEATURE_3DNOW),
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[3] =
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__ins_bit(3, X86_FEATURE_REP_GOOD) |
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__ins_bit(3, X86_FEATURE_NOPL),
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[4] =
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__ins_bit(4, X86_FEATURE_XMM3) |
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__ins_bit(4, X86_FEATURE_PCLMULQDQ) |
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__ins_bit(4, X86_FEATURE_MWAIT) |
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__ins_bit(4, X86_FEATURE_SSSE3) |
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__ins_bit(4, X86_FEATURE_CX16) |
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__ins_bit(4, X86_FEATURE_XMM4_1) |
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__ins_bit(4, X86_FEATURE_XMM4_2) |
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__ins_bit(4, X86_FEATURE_MOVBE) |
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__ins_bit(4, X86_FEATURE_POPCNT) |
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__ins_bit(4, X86_FEATURE_AES) |
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__ins_bit(4, X86_FEATURE_XSAVE) |
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__ins_bit(4, X86_FEATURE_OSXSAVE) |
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__ins_bit(4, X86_FEATURE_AVX) |
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__ins_bit(4, X86_FEATURE_F16C) |
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__ins_bit(4, X86_FEATURE_RDRAND),
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[6] =
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__ins_bit(6, X86_FEATURE_ABM) |
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__ins_bit(6, X86_FEATURE_SSE4A) |
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__ins_bit(6, X86_FEATURE_MISALIGNSSE) |
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__ins_bit(6, X86_FEATURE_3DNOWPREFETCH) |
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__ins_bit(6, X86_FEATURE_XOP) |
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__ins_bit(6, X86_FEATURE_FMA4) |
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__ins_bit(6, X86_FEATURE_TBM),
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[9] =
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__ins_bit(9, X86_FEATURE_FSGSBASE) |
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__ins_bit(9, X86_FEATURE_BMI1) |
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__ins_bit(9, X86_FEATURE_HLE) |
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__ins_bit(9, X86_FEATURE_AVX2) |
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__ins_bit(9, X86_FEATURE_BMI2) |
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__ins_bit(9, X86_FEATURE_ERMS) |
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__ins_bit(9, X86_FEATURE_RTM) |
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__ins_bit(9, X86_FEATURE_MPX) |
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__ins_bit(9, X86_FEATURE_AVX512F) |
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__ins_bit(9, X86_FEATURE_AVX512DQ) |
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__ins_bit(9, X86_FEATURE_RDSEED) |
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__ins_bit(9, X86_FEATURE_ADX) |
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__ins_bit(9, X86_FEATURE_CLFLUSHOPT) |
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__ins_bit(9, X86_FEATURE_AVX512PF) |
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__ins_bit(9, X86_FEATURE_AVX512ER) |
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__ins_bit(9, X86_FEATURE_AVX512CD) |
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__ins_bit(9, X86_FEATURE_SHA) |
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__ins_bit(9, X86_FEATURE_AVX512BW) |
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__ins_bit(9, X86_FEATURE_AVXVL),
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[10] =
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__ins_bit(10, X86_FEATURE_XSAVEOPT) |
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__ins_bit(10, X86_FEATURE_XSAVEC) |
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__ins_bit(10, X86_FEATURE_XGETBV1) |
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__ins_bit(10, X86_FEATURE_XSAVES),
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[11] =
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__ins_bit(11, X86_FEATURE_PREFETCHWT1),
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};
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#undef __ins_bit
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static int cpu_validate_ins_features(CpuinfoX86Entry *img_x86_entry)
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{
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size_t i;
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for (i = 0; i < ARRAY_SIZE(rt_cpu_info.x86_capability); i++) {
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u32 s = img_x86_entry->capability[i] & x86_ins_capability_mask[i];
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u32 d = rt_cpu_info.x86_capability[i] & x86_ins_capability_mask[i];
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/*
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* Destination might be more feature rich
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* but not the reverse.
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*/
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if (s & ~d) {
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pr_err("CPU instruction capabilities do not match run time\n");
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return -1;
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}
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}
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return 0;
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}
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static int cpu_validate_features(CpuinfoX86Entry *img_x86_entry)
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{
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if (img_x86_entry->n_capability != ARRAY_SIZE(rt_cpu_info.x86_capability)) {
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/*
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* Image carries different number of bits.
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* Simply reject, we can't guarantee anything
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* in such case.
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*/
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pr_err("Size of features in image mismatch "
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"one provided by run time CPU (%d:%d)\n",
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(unsigned)img_x86_entry->n_capability,
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(unsigned)ARRAY_SIZE(rt_cpu_info.x86_capability));
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return -1;
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}
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if (opts.cpu_cap == CPU_CAP_FPU) {
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/*
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* If we're requested to check FPU only ignore
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* any other bit. It's up to a user if the
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* rest of mismatches won't cause problems.
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*/
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#define __mismatch_fpu_bit(__bit) \
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(test_bit(__bit, (void *)img_x86_entry->capability) && \
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!cpu_has_feature(__bit))
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if (__mismatch_fpu_bit(X86_FEATURE_FPU) ||
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__mismatch_fpu_bit(X86_FEATURE_FXSR) ||
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__mismatch_fpu_bit(X86_FEATURE_XSAVE)) {
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pr_err("FPU feature required by image "
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"is not supported on host.\n");
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return -1;
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} else
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return 0;
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#undef __mismatch_fpu_bit
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}
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/*
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* Capability on instructions level only.
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*/
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if (opts.cpu_cap == CPU_CAP_INS)
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return cpu_validate_ins_features(img_x86_entry);
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/*
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* Strict capability mode. Everything must match.
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*/
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if (memcmp(img_x86_entry->capability, rt_cpu_info.x86_capability,
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sizeof(rt_cpu_info.x86_capability))) {
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pr_err("CPU capabilites do not match run time\n");
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return -1;
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}
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return 0;
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}
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int cpu_validate_cpuinfo(void)
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{
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CpuinfoX86Entry *img_x86_entry;
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CpuinfoEntry *img_cpu_info;
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struct cr_img *img;
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int ret = -1;
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img = open_image(CR_FD_CPUINFO, O_RSTR);
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if (!img)
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return -1;
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if (pb_read_one(img, &img_cpu_info, PB_CPUINFO) < 0)
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goto err;
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if (img_cpu_info->n_x86_entry != 1) {
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pr_err("No x86 related cpuinfo in image, "
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"corruption (n_x86_entry = %zi)\n",
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img_cpu_info->n_x86_entry);
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goto err;
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}
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img_x86_entry = img_cpu_info->x86_entry[0];
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if (img_x86_entry->vendor_id != CPUINFO_X86_ENTRY__VENDOR__INTEL &&
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img_x86_entry->vendor_id != CPUINFO_X86_ENTRY__VENDOR__AMD) {
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pr_err("Unknown cpu vendor %d\n", img_x86_entry->vendor_id);
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goto err;
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}
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|
|
if (img_x86_entry->n_capability != ARRAY_SIZE(rt_cpu_info.x86_capability)) {
|
|
pr_err("Image carries %u words while %u expected\n",
|
|
(unsigned)img_x86_entry->n_capability,
|
|
(unsigned)ARRAY_SIZE(rt_cpu_info.x86_capability));
|
|
goto err;
|
|
}
|
|
|
|
ret = cpu_validate_features(img_x86_entry);
|
|
err:
|
|
close_image(img);
|
|
return ret;
|
|
}
|
|
|
|
int cpuinfo_dump(void)
|
|
{
|
|
if (cpu_init())
|
|
return -1;
|
|
if (cpu_dump_cpuinfo())
|
|
return -1;
|
|
return 0;
|
|
}
|
|
|
|
int cpuinfo_check(void)
|
|
{
|
|
if (cpu_init())
|
|
return 1;
|
|
|
|
/*
|
|
* Force to check all caps if empty passed,
|
|
* still allow to check instructions only
|
|
* and etc.
|
|
*/
|
|
if (!opts.cpu_cap)
|
|
opts.cpu_cap = CPU_CAP_ALL;
|
|
|
|
if (cpu_validate_cpuinfo())
|
|
return 1;
|
|
|
|
return 0;
|
|
}
|