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https://github.com/checkpoint-restore/criu.git
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303b875892
This patch initiates the ppc64le architecture support in CRIU. Note that ppc64 (Big Endian) architecture is not yet supported since there are still several issues to address with this architecture. However, in the long term, the two architectures should be addressed using the almost the same code, so sharing the ppc64 directory. Major ppc64 issues: Loader is not involved when the parasite code is loaded. So no relocation is done for the parasite code. As a consequence r2 must be set manually when entering the parasite code, and GOT is not filled. Furthermore, the r2 fixup code at the services's global address which has not been fixed by the loader should not be run. Branching at local address, as the assembly code does is jumping over it. On the long term, relocation should be done when loading the parasite code. We are introducing 2 trampolines for the 2 entry points of the restorer blob. These entry points are dealing with r2. These ppc64 specific entry points are overwritting the standard one in sigreturn_restore() from cr-restore.c. Instead of using #ifdef, we may introduce a per arch wrapper here. CRIU needs 2 kernel patches to be run powerpc which are not yet upstream: - Tracking the vDSO remapping - Enabling the kcmp system call on powerpc Feature not yet supported: - Altivec registers C/R - VSX registers C/R - TM support - all lot of things I missed.. Signed-off-by: Laurent Dufour <ldufour@linux.vnet.ibm.com> Signed-off-by: Pavel Emelyanov <xemul@parallels.com>
112 lines
2.1 KiB
C
112 lines
2.1 KiB
C
#ifndef __CR_ATOMIC_H__
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#define __CR_ATOMIC_H__
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/*
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* PowerPC atomic operations
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*
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* Copied from kernel header file arch/powerpc/include/asm/atomic.h
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*/
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typedef struct {
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int counter;
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} atomic_t;
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#include "asm/cmpxchg.h"
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#define PPC_ATOMIC_ENTRY_BARRIER "lwsync \n"
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#define PPC_ATOMIC_EXIT_BARRIER "sync \n"
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#define ATOMIC_INIT(i) { (i) }
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static __inline__ int atomic_read(const atomic_t *v)
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{
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int t;
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__asm__ __volatile__("lwz%U1%X1 %0,%1" : "=r"(t) : "m"(v->counter));
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return t;
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}
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static __inline__ void atomic_set(atomic_t *v, int i)
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{
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__asm__ __volatile__("stw%U0%X0 %1,%0" : "=m"(v->counter) : "r"(i));
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}
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#define ATOMIC_OP(op, asm_op) \
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static __inline__ void atomic_##op(int a, atomic_t *v) \
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{ \
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int t; \
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\
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__asm__ __volatile__( \
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"1: lwarx %0,0,%3 # atomic_" #op "\n" \
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#asm_op " %0,%2,%0\n" \
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" stwcx. %0,0,%3 \n" \
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" bne- 1b\n" \
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: "=&r" (t), "+m" (v->counter) \
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: "r" (a), "r" (&v->counter) \
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: "cc"); \
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} \
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ATOMIC_OP(add, add)
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ATOMIC_OP(sub, subf)
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#undef ATOMIC_OP
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static __inline__ void atomic_inc(atomic_t *v)
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{
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int t;
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__asm__ __volatile__(
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"1: lwarx %0,0,%2 # atomic_inc\n\
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addic %0,%0,1\n"
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" stwcx. %0,0,%2 \n\
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bne- 1b"
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: "=&r" (t), "+m" (v->counter)
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: "r" (&v->counter)
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: "cc", "xer");
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}
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static __inline__ int atomic_inc_return(atomic_t *v)
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{
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int t;
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__asm__ __volatile__(
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PPC_ATOMIC_ENTRY_BARRIER \
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"1: lwarx %0,0,%1 # atomic_inc_return\n\
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addic %0,%0,1\n"
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" stwcx. %0,0,%1 \n\
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bne- 1b \n" \
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PPC_ATOMIC_EXIT_BARRIER
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: "=&r" (t)
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: "r" (&v->counter)
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: "cc", "xer", "memory");
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return t;
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}
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/*
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* atomic_inc_and_test - increment and test
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* @v: pointer of type atomic_t
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*
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* Atomically increments @v by 1
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* and returns true if the result is zero, or false for all
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* other cases.
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*/
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static __inline__ void atomic_dec(atomic_t *v)
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{
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int t;
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__asm__ __volatile__(
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"1: lwarx %0,0,%2 # atomic_dec\n\
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addic %0,%0,-1\n"
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" stwcx. %0,0,%2\n\
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bne- 1b"
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: "=&r" (t), "+m" (v->counter)
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: "r" (&v->counter)
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: "cc", "xer");
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}
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#define atomic_cmpxchg(v, o, n) (cmpxchg(&((v)->counter), (o), (n)))
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#endif /* __CR_ATOMIC_H__ */
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