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https://github.com/checkpoint-restore/criu.git
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4ebfa9813b
The Power 8 introduces the transactional memory (TM) operations (see Power ISA 3.0 for details). The support for the transactional memory operation during the checkpoint and restart requires extended ptrace API provided by the kernel 4.8. When checkpointing a thread while a transactional memory operation is in progress, the TM checkpointed state is checkpointed through the new ptrace API. If these new APIs are not available, the checkpoint is aborted and an explicit error is reported. At restart time, the TM state is pushed on the stack frame to be reloaded by the kernel when reading the stack frame. Only suspended TM operation could be checkpointed since active one will be aborted once a system call is made. Suspended operation will be aborted as well, and the checkpointed thread is expected to handle the TM failure as usual (retrying is a good option). Signed-off-by: Laurent Dufour <ldufour@linux.vnet.ibm.com> Reviewed-by: Dmitry Safonov <dsafonov@virtuozzo.com> Signed-off-by: Pavel Emelyanov <xemul@virtuozzo.com>
69 lines
2 KiB
Protocol Buffer
69 lines
2 KiB
Protocol Buffer
syntax = "proto2";
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message user_ppc64_regs_entry {
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/* Following is the list of regiters starting at r0. */
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repeated uint64 gpr = 1;
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required uint64 nip = 2;
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required uint64 msr = 3;
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required uint64 orig_gpr3 = 4;
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required uint64 ctr = 5;
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required uint64 link = 6;
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required uint64 xer = 7;
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required uint64 ccr = 8;
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required uint64 trap = 9;
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/* For Transactional memory support since P8 */
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optional uint64 texasr = 10;
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optional uint64 tfhar = 11;
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optional uint64 tfiar = 12;
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}
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message user_ppc64_fpstate_entry {
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/* Following is the list of regiters starting at fpr0 */
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repeated uint64 fpregs = 1;
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}
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message user_ppc64_vrstate_entry {
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/*
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* Altivec registers
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* The vector registers are 128bit registers (VSR[32..63]).
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* The following vregs entry will store first the high part then the
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* low one:
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* VR0 = vrregs[0] << 64 | vrregs[1];
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* VR1 = vrregs[2] << 64 | vrregs[3];
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* ..
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* The last entry stores in a 128bit field the VSCR which is a 32bit
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* value returned by the kernel in a 128 field.
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*/
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repeated uint64 vrregs = 1;
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required uint32 vrsave = 2;
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}
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message user_ppc64_vsxstate_entry {
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/*
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* VSX registers
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* The vector-scale registers are 128bit registers (VSR[0..64]).
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* Since there is an overlapping over the VSX registers by the FPR and
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* the Altivec registers, only the lower part of the first 32 VSX
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* registers have to be saved.
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*/
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repeated uint64 vsxregs = 1;
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}
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/*
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* Transactional memory operation's state
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*/
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message user_ppc64_tm_regs_entry {
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required user_ppc64_regs_entry gpregs = 1;
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optional user_ppc64_fpstate_entry fpstate = 2;
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optional user_ppc64_vrstate_entry vrstate = 3;
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optional user_ppc64_vsxstate_entry vsxstate = 4;
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}
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message thread_info_ppc64 {
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required uint64 clear_tid_addr = 1;
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required user_ppc64_regs_entry gpregs = 2;
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optional user_ppc64_fpstate_entry fpstate = 3;
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optional user_ppc64_vrstate_entry vrstate = 4;
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optional user_ppc64_vsxstate_entry vsxstate = 5;
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optional user_ppc64_tm_regs_entry tmstate = 6;
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}
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