mirror of
https://github.com/checkpoint-restore/criu.git
synced 2026-07-22 09:39:13 +00:00
55370b720e
Store BO contents directly to file (1 per GPU) instead of using protobuf. Bug Fix: Fixes an issue where we could not handle BOs bigger than 4GB because protobuf has an internal limit of 4GB for the Bytes structure. Performance Improvements: This significantly reduces CR duration on multi-GPU systems as it allows reading and writing to disk in parallel. During checkpoint, instead of waiting for all the BO contents to be read from the one protobuf file, we can now start writing the BO contents as soon as the first BO is read from disk. During restore, we can start writing BO contents to disk after the first BO from VRAM. This also reduces the peak amount of system memory used as we only need to keep 1 BO content in memory per GPU at a time instead of all the BO contents. Signed-off-by: David Yat Sin <david.yatsin@amd.com>
66 lines
1.9 KiB
Protocol Buffer
66 lines
1.9 KiB
Protocol Buffer
syntax = "proto2";
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message dev_iolink {
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required uint32 type = 1;
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required uint32 node_to_id = 2;
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}
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message device_entry {
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required uint32 node_id = 1;
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required uint32 gpu_id = 2;
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required uint32 cpu_cores_count = 3;
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required uint32 simd_count = 4;
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required uint32 mem_banks_count = 5;
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required uint32 caches_count = 6;
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required uint32 io_links_count = 7;
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required uint32 max_waves_per_simd = 8;
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required uint32 lds_size_in_kb = 9;
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required uint32 gds_size_in_kb = 10;
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required uint32 num_gws = 11;
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required uint32 wave_front_size = 12;
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required uint32 array_count = 13;
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required uint32 simd_arrays_per_engine = 14;
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required uint32 cu_per_simd_array = 15;
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required uint32 simd_per_cu = 16;
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required uint32 max_slots_scratch_cu = 17;
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required uint32 vendor_id = 18;
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required uint32 device_id = 19;
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required uint32 domain = 20;
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required uint32 drm_render_minor = 21;
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required uint64 hive_id = 22;
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required uint32 num_sdma_engines = 23;
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required uint32 num_sdma_xgmi_engines = 24;
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required uint32 num_sdma_queues_per_engine = 25;
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required uint32 num_cp_queues = 26;
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required uint32 fw_version = 27;
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required uint32 capability = 28;
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required uint32 sdma_fw_version = 29;
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required uint32 vram_public = 30;
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required uint64 vram_size = 31;
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repeated dev_iolink iolinks = 32;
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}
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message bo_entry {
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required uint64 addr = 1;
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required uint64 size = 2;
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required uint64 offset = 3;
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required uint32 alloc_flags = 4;
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required uint32 gpu_id = 5;
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}
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message criu_kfd {
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required uint32 pid = 1;
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required uint32 num_of_gpus = 2;
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required uint32 num_of_cpus = 3;
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repeated device_entry device_entries = 4;
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required uint64 num_of_bos = 5;
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repeated bo_entry bo_entries = 6;
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required uint32 num_of_objects = 7;
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required uint64 shared_mem_size = 8;
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required uint32 shared_mem_magic = 9;
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required bytes priv_data = 10;
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}
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message criu_render_node {
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required uint32 gpu_id = 1;
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}
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