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https://github.com/checkpoint-restore/criu.git
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coredump: enable coredump generation on riscv64
Wire riscv64 CRIU core data into the Python coredump generator. Set EM_RISCV in the ELF header, map GP registers for NT_PRSTATUS, map FP registers for NT_FPREGSET, and enable the existing smoke test on riscv64. The layout follows the current CRIU riscv64 core format and the Linux RISC-V user ABI. Partially addresses #2433. Signed-off-by: Shaurya Rane <ssrane_b23@ee.vjti.ac.in>
This commit is contained in:
Shaurya Rane
Radostin Stoyanov
parent
c70a4b3848
commit
7539f399fe
4 changed files with 89 additions and 4 deletions
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@ -6,7 +6,7 @@ import sys
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import criu_coredump
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PLATFORMS = ["aarch64", "armv7l", "x86_64"]
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PLATFORMS = ["aarch64", "armv7l", "riscv64", "x86_64"]
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def coredump(opts):
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@ -141,6 +141,7 @@ class coredump_generator:
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thread_info_key = {
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"aarch64": "ti_aarch64",
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"armv7l": "ti_arm",
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"riscv64": "ti_riscv64",
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"x86_64": "thread_info",
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}
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@ -259,6 +260,7 @@ class coredump_generator:
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e_machine_dict = {
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"aarch64": elf.EM_AARCH64,
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"armv7l": elf.EM_ARM,
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"riscv64": elf.EM_RISCV,
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"x86_64": elf.EM_X86_64,
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}
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return e_machine_dict[self.machine]
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@ -463,6 +465,39 @@ class coredump_generator:
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pr_reg.es = regs["es"]
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pr_reg.fs = regs["fs"]
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pr_reg.gs = regs["gs"]
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elif self.machine == "riscv64":
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pr_reg.pc = regs["pc"]
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pr_reg.ra = regs["ra"]
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pr_reg.sp = regs["sp"]
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pr_reg.gp = regs["gp"]
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pr_reg.tp = regs["tp"]
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pr_reg.t0 = regs["t0"]
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pr_reg.t1 = regs["t1"]
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pr_reg.t2 = regs["t2"]
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pr_reg.s0 = regs["s0"]
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pr_reg.s1 = regs["s1"]
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pr_reg.a0 = regs["a0"]
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pr_reg.a1 = regs["a1"]
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pr_reg.a2 = regs["a2"]
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pr_reg.a3 = regs["a3"]
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pr_reg.a4 = regs["a4"]
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pr_reg.a5 = regs["a5"]
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pr_reg.a6 = regs["a6"]
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pr_reg.a7 = regs["a7"]
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pr_reg.s2 = regs["s2"]
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pr_reg.s3 = regs["s3"]
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pr_reg.s4 = regs["s4"]
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pr_reg.s5 = regs["s5"]
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pr_reg.s6 = regs["s6"]
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pr_reg.s7 = regs["s7"]
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pr_reg.s8 = regs["s8"]
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pr_reg.s9 = regs["s9"]
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pr_reg.s10 = regs["s10"]
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pr_reg.s11 = regs["s11"]
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pr_reg.t3 = regs["t3"]
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pr_reg.t4 = regs["t4"]
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pr_reg.t5 = regs["t5"]
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pr_reg.t6 = regs["t6"]
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def _gen_fpregset(self, pid, tid):
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"""
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@ -492,7 +527,7 @@ class coredump_generator:
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"""
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Get the floating point register dictionary based on the current architecture.
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"""
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fpregs_key_dict = {"aarch64": "fpsimd", "x86_64": "fpregs"}
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fpregs_key_dict = {"aarch64": "fpsimd", "riscv64": "fpsimd", "x86_64": "fpregs"}
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fpregs_key = fpregs_key_dict[self.machine]
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thread_info_key = self.thread_info_key[self.machine]
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@ -507,6 +542,9 @@ class coredump_generator:
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fpregset.vregs = (ctypes.c_ulonglong * len(regs["vregs"]))(*regs["vregs"])
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fpregset.fpsr = regs["fpsr"]
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fpregset.fpcr = regs["fpcr"]
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elif self.machine == "riscv64":
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fpregset.f = (ctypes.c_ulonglong * len(regs["f"]))(*regs["f"])
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fpregset.fcsr = regs["fcsr"]
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elif self.machine == "x86_64":
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fpregset.cwd = regs["cwd"]
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fpregset.swd = regs["swd"]
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@ -53,6 +53,7 @@ ET_CORE = 4 # #define ET_CORE 4 /* Core file */
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EM_ARM = 40 # #define EM_ARM 40 /* ARM */
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EM_X86_64 = 62 # #define EM_X86_64 62 /* AMD x86-64 architecture */
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EM_AARCH64 = 183 # #define EM_AARCH64 183 /* ARM AARCH64 */
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EM_RISCV = 243 # #define EM_RISCV 243 /* RISC-V */
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# Legal values for e_version (version).
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EV_CURRENT = 1 # #define EV_CURRENT 1 /* Current version */
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@ -461,12 +462,50 @@ class arm_user_regs_struct(ctypes.Structure): # struct arm_user_regs_struct
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]
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class riscv64_user_regs_struct(ctypes.Structure): # struct user_regs_struct
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_fields_ = [
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("pc", ctypes.c_ulonglong),
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("ra", ctypes.c_ulonglong),
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("sp", ctypes.c_ulonglong),
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("gp", ctypes.c_ulonglong),
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("tp", ctypes.c_ulonglong),
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("t0", ctypes.c_ulonglong),
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("t1", ctypes.c_ulonglong),
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("t2", ctypes.c_ulonglong),
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("s0", ctypes.c_ulonglong),
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("s1", ctypes.c_ulonglong),
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("a0", ctypes.c_ulonglong),
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("a1", ctypes.c_ulonglong),
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("a2", ctypes.c_ulonglong),
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("a3", ctypes.c_ulonglong),
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("a4", ctypes.c_ulonglong),
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("a5", ctypes.c_ulonglong),
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("a6", ctypes.c_ulonglong),
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("a7", ctypes.c_ulonglong),
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("s2", ctypes.c_ulonglong),
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("s3", ctypes.c_ulonglong),
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("s4", ctypes.c_ulonglong),
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("s5", ctypes.c_ulonglong),
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("s6", ctypes.c_ulonglong),
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("s7", ctypes.c_ulonglong),
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("s8", ctypes.c_ulonglong),
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("s9", ctypes.c_ulonglong),
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("s10", ctypes.c_ulonglong),
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("s11", ctypes.c_ulonglong),
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("t3", ctypes.c_ulonglong),
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("t4", ctypes.c_ulonglong),
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("t5", ctypes.c_ulonglong),
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("t6", ctypes.c_ulonglong),
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]
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# elf_greg_t = ctypes.c_ulonglong
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# ELF_NGREG = ctypes.sizeof(user_regs_struct)/ctypes.sizeof(elf_greg_t)
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# elf_gregset_t = elf_greg_t*ELF_NGREG
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user_regs_dict = {
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"aarch64": aarch64_user_regs_struct,
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"armv7l": arm_user_regs_struct,
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"riscv64": riscv64_user_regs_struct,
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"x86_64": x86_64_user_regs_struct,
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}
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@ -653,9 +692,17 @@ class aarch64_user_fpregs_struct(ctypes.Structure): # struct aarch64_user_fpreg
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]
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class riscv64_user_fpregs_struct(ctypes.Structure): # struct __riscv_d_ext_state
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_fields_ = [
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("f", ctypes.c_ulonglong * 32),
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("fcsr", ctypes.c_uint),
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]
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user_fpregs_dict = {
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"aarch64": aarch64_user_fpregs_struct,
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"armv7l": None,
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"riscv64": riscv64_user_fpregs_struct,
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"x86_64": x86_64_user_fpregs_struct,
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}
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@ -45,8 +45,8 @@ function run_test {
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UNAME_M=$(uname -m)
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if [[ "$UNAME_M" != "aarch64" && "$UNAME_M" != "armv7l" &&"$UNAME_M" != "x86_64" ]]; then
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echo "criu-coredump only supports aarch64 armv7l, and x86_64. skipping."
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if [[ "$UNAME_M" != "aarch64" && "$UNAME_M" != "armv7l" && "$UNAME_M" != "riscv64" && "$UNAME_M" != "x86_64" ]]; then
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echo "criu-coredump only supports aarch64, armv7l, riscv64, and x86_64. skipping."
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exit 0
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fi
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