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x86/asm: update test_bit() and test_and_set_bit()

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Build on Fedora Core 33 produces the following warnings:

include/common/asm/bitops.h: Assembler messages:
include/common/asm/bitops.h:37: Warning: no instruction mnemonic suffix given and no register operands; using default for `bt'
include/common/asm/bitops.h: Assembler messages:
include/common/asm/bitops.h:63: Warning: no instruction mnemonic suffix given and no register operands; using default for `bts'

Update test_bit() and test_and_set_bit() implementation with recent
version from the Linux kernel to fix the warning.

Fixes #1217
Reported-by: Adrian Reber <areber@redhat.com>
Signed-off-by: Mike Rapoport <rppt@linux.ibm.com>
This commit is contained in:
Mike Rapoport 2020-10-12 10:05:39 +03:00 • committed by Andrei Vagin
parent c7726b7f35
commit 1062cc4fed
1 changed files with 21 additions and 11 deletions
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32
include/common/arch/x86/asm/bitops.h
View file

@ -1,9 +1,18 @@
#ifndef __CR_BITOPS_H__
#define __CR_BITOPS_H__
#include <stdbool.h>
#include "common/arch/x86/asm/cmpxchg.h"
#include "common/asm/bitsperlong.h"
#ifdef __GCC_ASM_FLAG_OUTPUTS__
# define CC_SET(c) "\n\t/* output condition code " #c "*/\n"
# define CC_OUT(c) "=@cc" #c
#else
# define CC_SET(c) "\n\tset" #c " %[_cc_" #c "]\n"
# define CC_OUT(c) [_cc_ ## c] "=qm"
#endif
#define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d))
#define BITS_TO_LONGS(nr) DIV_ROUND_UP(nr, BITS_PER_LONG)
@ -30,14 +39,14 @@ static inline void change_bit(int nr, volatile unsigned long *addr)
asm volatile("btcl %1,%0" : ADDR : "Ir" (nr));
}
static inline int test_bit(int nr, volatile const unsigned long *addr)
static inline bool test_bit(long nr, volatile const unsigned long *addr)
{
int oldbit;
bool oldbit;
asm volatile("bt %2,%1\n\t"
"sbb %0,%0"
: "=r" (oldbit)
: "m" (*(unsigned long *)addr), "Ir" (nr));
asm volatile("btq %2,%1"
CC_SET(c)
: CC_OUT(c) (oldbit)
: "m" (*(unsigned long *)addr), "Ir" (nr) : "memory");
return oldbit;
}
@ -55,13 +64,14 @@ static inline void clear_bit(int nr, volatile unsigned long *addr)
* This operation is atomic and cannot be reordered.
* It also implies a memory barrier.
*/
static inline int test_and_set_bit(int nr, volatile unsigned long *addr)
static inline bool test_and_set_bit(int nr, volatile unsigned long *addr)
{
int oldbit;
asm volatile(LOCK_PREFIX "bts %2,%1\n\t"
"sbb %0,%0" : "=r" (oldbit), ADDR : "Ir" (nr) : "memory");
bool oldbit;
asm("btsq %2,%1"
CC_SET(c)
: CC_OUT(c) (oldbit)
: "m" (*(unsigned long *)addr), "Ir" (nr) : "memory");
return oldbit;
}